https://peertube.watch/videos/watch/2d6f883a-2edb-4700-a6fe-4a2adef9b6dd The Libre-SOC project has been prototyped using an Lattice ECP5 FPGA before its first tapeout. Since then many things have changed. One big change is the use of a different controller for DDR3 called gram. To get DDR3 working on the OrangeCrab many changes are needed. This talk will provide an overview on my work on Libre-SOC in the past two years, an overview of DDR SDRAM interfaces and the PHYs commonly found on FPGAs and some ways to debug the OrangeCrab using a BeagleWire. Speaker: Tobias Platen (they/them), Track: Libre-SOC, FPGA and VLSI devroom, Room: K.4.201, When: Saturday 3 February 2024, 13:40–14:30 (Brussels time), Schedule: FOSDEM 2024 event page, Slides & links Presentation Slide Deck (slides), Project Homepage, the Libre-SOC Project source repositories, gram the DRAM library, Licence: Creative Commons Attribution 2.0 Belgium (CC BY 2.0 BE) (as stated in the FOSDEM video archive). Attribution: “Using the ECP5 for Libre-SOC prototyping” by Tobias Platen (they/them), FOSDEM 2024. Original recording: 2024/k4201/fosdem-2024-2060-using-the-ecp5-for-libre-soc-prototyping.av1.webm from the FOSDEM video archive. This channel is an unofficial mirror; FOSDEM is a free and non-commercial event organised by the community for the community. Tue, 20 Oct 2026 22:15:49 GMT https://validator.w3.org/feed/docs/rss2.html PeerTube - https://peertube.watch https://peertube.watch/lazy-static/avatars/3b284627-b75f-409e-ac2e-10f4c2946f43.png https://peertube.watch/videos/watch/2d6f883a-2edb-4700-a6fe-4a2adef9b6dd All rights reserved, unless otherwise specified in the terms specified at https://peertube.watch/about and potential licenses granted by each content's rightholder.