https://peertube.watch/videos/watch/2db98d58-72b3-4501-a947-7a4373759db0 Formal verification, or formal correctness proofs, are powerful tools when designing your FPGA or ASIC "gateware". They help finding bugs sometimes missed in simulation, triggered by corner cases you didn't think to check. This talk will give a little background on how they work, the available ecosystem of tools, show some small examples on how to use them, and some practical results from real-life usage. Speaker: Cesar Strauss, Track: Libre-SOC, FPGA and VLSI devroom, Room: K.4.201, When: Saturday 3 February 2024, 11:25–12:05 (Brussels time), Schedule: FOSDEM 2024 event page, Slides & links Slides (final), LibreSOC main site, LibreSOC soc formal verification source code, Licence: Creative Commons Attribution 2.0 Belgium (CC BY 2.0 BE) (as stated in the FOSDEM video archive). Attribution: “An introduction to Formal Verification of Digital Circuits” by Cesar Strauss, FOSDEM 2024. Original recording: 2024/k4201/fosdem-2024-2215-an-introduction-to-formal-verification-of-digital-circuits.av1.webm from the FOSDEM video archive. This channel is an unofficial mirror; FOSDEM is a free and non-commercial event organised by the community for the community. Thu, 15 Oct 2026 07:02:50 GMT https://validator.w3.org/feed/docs/rss2.html PeerTube - https://peertube.watch https://peertube.watch/lazy-static/avatars/3b284627-b75f-409e-ac2e-10f4c2946f43.png https://peertube.watch/videos/watch/2db98d58-72b3-4501-a947-7a4373759db0 All rights reserved, unless otherwise specified in the terms specified at https://peertube.watch/about and potential licenses granted by each content's rightholder.